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1 ltc1871 wide input range, no r sense tm current mode boost, flyback and sepic controller the ltc ? 1871 is a wide input range, current mode, boost, flyback and sepic controller that drives an n-channel power mosfet and requires very few external compo- nents. intended for low to medium power applications, it eliminates the need for a current sense resistor by utiliz- ing the power mosfets on-resistance, thereby maximiz- ing efficiency. the ics operating frequency can be set with an external resistor over a 50khz to 1mhz range, and can be synchro- nized to an external clock using the mode/sync pin. burst mode operation at light loads, a low minimum operating supply voltage of 2.5v and a low shutdown quiescent current of 10 m a make the ltc1871 ideally suited for battery-operated systems. for applications requiring constant frequency operation, burst mode operation can be defeated using the mode/ sync pin. higher output voltage boost, sepic and fly- back applications are possible with the ltc1871 by connecting the sense pin to a resistor in the source of the power mosfet. the ltc1871 is available in the 10-lead msop package. n high efficiency (no sense resistor required) n wide input voltage range: 2.5v to 36v n current mode control provides excellent transient response n high maximum duty cycle (92% typ) n 2% run pin threshold with 100mv hysteresis n 1% internal voltage reference n micropower shutdown: i q = 10 m a n programmable operating frequency (50khz to 1mhz) with one external resistor n synchronizable to an external clock up to 1.3 f osc n user-controlled pulse skip or burst mode ? operation n internal 5.2v low dropout voltage regulator n output overvoltage protection n capable of operating with a sense resistor for high output voltage applications n small 10-lead msop package n telecom power supplies n portable electronic equipment burst mode is a registered trademark of linear technology corporation. no r sense is a trademark of linear technology corporation. figure 1. high efficiency 3.3v input, 5v output boost converter (bootstrapped) efficiency of figure 1 , ltc and lt are registered trademarks of linear technology corporation. output current (a) 30 efficiency (%) 90 100 80 50 70 60 40 0.001 0.1 1 10 1871 f01b 0.01 burst mode operation pulse-skip mode descriptio u features applicatio s u typical applicatio u + run i th fb freq mode/sync sense v in intv cc gate gnd ltc1871 r t 80.6k 1% r2 37.4k 1% r1 12.1k 1% c vcc 4.7 f x5r c in 22 f 6.3v 2 m1 d1 l1 1 h r c 22k c c1 6.8nf c c2 47pf c out1 150 f 6.3v 4 v in 3.3v v out 5v 7a (10a peak) gnd 1871 f01a + c out2 22 f 6.3v x5r 2 c in : taiyo yuden jmk325bj226mm c out1 : panasonic eefueoj151r c out2 : taiyo yuden jmk325bj226mm d1: mbrb2515l l1: sumida cep125-h 1r0mh m1: fairchild fds7760a
2 ltc1871 (note 1) v in voltage ............................................... C 0.3v to 36v intv cc voltage ........................................... C 0.3v to 7v intv cc output current ........................................ 50ma gate voltage ........................... C 0.3v to v intvcc + 0.3v i th , fb voltages ....................................... C 0.3v to 2.7v run, mode/sync voltages ....................... C 0.3v to 7v freq voltage ............................................C 0.3v to 1.5v sense pin voltage ................................... C 0.3v to 36v operating temperature range (note 2) .. C 40 c to 85 c junction temperature (note 3) ............................ 125 c storage temperature range ................. C 65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c order part number LTC1871EMS t jmax = 125 c, q ja = 120 c/ w absolute axi u rati gs w ww u package/order i for atio uu w electrical characteristics ms part marking ltsx 1 2 3 4 5 run i th fb freq mode/ sync 10 9 8 7 6 sense v in intv cc gate gnd top view ms package 10-lead plastic msop symbol parameter conditions min typ max units main control loop v in(min) minimum input voltage 2.5 v i q input voltage supply current (note 4) continuous mode v mode/sync = 5v, v fb = 1.4v, v ith = 0.75v 550 1000 m a burst mode operation, no load v mode/sync = 0v, v ith = 0.2v (note 5) 250 500 m a shutdown mode v run = 0v 10 20 m a v run + rising run input threshold voltage 1.348 v v run C falling run input threshold voltage 1.223 1.248 1.273 v l 1.198 1.298 v v run(hyst) run pin input threshold hysteresis 50 100 150 mv i run run input current 160 na v fb feedback voltage v ith = 0.2v (note 5) 1.218 1.230 1.242 v l 1.212 1.248 v i fb fb pin input current v ith = 0.2v (note 5) 18 60 na d v fb line regulation 2.5v v in 30v 0.002 0.02 %/v d v in d v fb load regulation v mode/sync = 0v, v th = 0.5v to 0.90v (note 5) l C1 C0.1 % d v ith d v fb(ov) d fb pin, overvoltage lockout v fb(ov) C v fb(nom) in percent 2.5 6 10 % g m error amplifier transconductance i th pin load = 5 m a (note 5) 650 m mho v ith(burst) burst mode operation i th pin voltage falling i th voltage (note 5) 0.3 v v sense(max) maximum current sense input threshold duty cycle < 20% 120 150 180 mv i sense(on) sense pin current (gate high) v sense = 0v 35 50 m a i sense(off) sense pin current (gate low) v sense = 30v 0.1 5 m a the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v in = v intvcc = 5v, v run = 1.5v, r freq = 80k, v mode/sync = 0v, unless otherwise specified. consult ltc marketing for parts specified with wider operating temperature ranges.
3 ltc1871 electrical characteristics note 1: absolute maximum ratings are those values beyond which the life of the device may be impaired. note 2: the ltc1871e is guaranteed to meet performance specifications from 0 c to 70 c. specifications over the C 40 c to 85 c operating temperature range are assured by design, characterization and correlation with statistical process controls. note 3: t j is calculated from the ambient temperature t a and power dissipation p d according to the following formula: t j = t a + (p d ? 120 c/w) note 4: the dynamic input supply current is higher due to power mosfet gate charging (q g ? f osc ). see applications information. note 5: the ltc1871 is tested in a feedback loop that servos v fb to the reference voltage with the i th pin forced to a voltage between 0v and 1.4v (the no load to full load operating voltage range for the i th pin is 0.3v to 1.23v). note 6: in a synchronized application, the internal slope compensation gain is increased by 25%. synchronizing to a significantly higher ratio will reduce the effective amount of slope compensation, which could result in subharmonic oscillation for duty cycles greater than 50%. note 7: rise and fall times are measured at 10% and 90% levels. the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v in = v intvcc = 5v, v run = 1.5v, r freq = 80k, v mode/sync = 0v, unless otherwise specified. symbol parameter conditions min typ max units oscillator f osc oscillator frequency r freq = 80k 250 300 350 khz oscillator frequency range 50 1000 khz d max maximum duty cycle 87 92 97 % f sync/ f osc recommended maximum synchronized f osc = 300khz (note 6) 1.25 1.30 frequency ratio t sync(min) mode/sync minimum input pulse width v sync = 0v to 5v 25 ns t sync(max) mode/sync maximum input pulse width v sync = 0v to 5v 0.8/f osc ns v il(mode) low level mode/sync input voltage 0.3 v v ih(mode) high level mode/sync input voltage 1.2 v r mode/sync mode/sync input pull-down resistance 50 k w v freq nominal freq pin voltage 0.62 v low dropout regulator v intvcc intv cc regulator output voltage v in = 7.5v 5.0 5.2 5.4 v d v intvcc intv cc regulator line regulation 7.5v v in 15v 8 25 mv d v in1 d v intvcc intv cc regulator line regulation 15v v in 30v 70 200 mv d v in2 v ldo(load) intv cc load regulation 0 i intvcc 20ma, v in = 7.5v C 2 C 0.2 % v dropout intv cc regulator dropout voltage v in = 5v, intv cc load = 20ma 280 mv i intvcc bootstrap mode intv cc supply run = 0v, sense = 5v 10 20 m a current in shutdown gate driver t r gate driver output rise time c l = 3300pf (note 7) 17 100 ns t f gate driver output fall time c l = 3300pf (note 7) 8 100 ns
4 ltc1871 typical perfor a ce characteristics uw fb voltage vs temp fb voltage line regulation fb pin current vs temperature temperature ( c) ?0 fb voltage (v) 1.23 1.24 150 1871 g01 1.22 1.21 0 50 100 ?5 25 75 125 1.25 v in (v) 0 1.229 fb voltage (v) 1.230 1.231 5101520 1871 g02 25 30 35 temperature ( c) ?0 0 fb pin current (na) 10 20 30 40 60 ?5 25 0 50 100 75 1871 g03 125 150 50 shutdown mode i q vs v in burst mode i q vs v in v in (v) 0 0 shutdown mode i q ( a) 10 20 10 20 30 40 1871 g04 30 shutdown mode i q vs temperature temperature ( c) ?0 0 shutdown mode i q ( a) 5 10 15 20 25 0 25 50 1871 g05 75 100 125 150 v in = 5v v in (v) 0 0 burst mode i q ( a) 100 200 300 400 600 10 20 1871 g06 30 40 500 burst mode i q vs temperature gate drive rise and fall time vs c l dynamic i q vs frequency temperature ( c) ?0 0 burst mode i q ( a) 200 500 0 50 75 1871 g07 100 400 300 ?5 25 100 125 150 frequency (khz) 0 0 i q (ma) 2 6 8 10 800 18 1871 g08 4 400 1200 600 200 1000 12 14 16 c l = 3300pf i q(tot) = 550 a + qg ?f c l (pf) 0 0 time (ns) 10 20 30 40 60 2000 4000 6000 8000 1871 g09 10000 12000 50 rise time fall time
5 ltc1871 typical perfor a ce characteristics uw run thresholds vs v in r t vs frequency frequency vs temperature sense pin current vs temperature maximum sense threshold vs temperature intv cc load regulation intv cc dropout voltage vs current, temperature intv cc line regulation v in (v) 0 1.2 run thresholds (v) 1.3 1.4 10 20 30 40 1871 g10 1.5 run thresholds vs temperature temperature ( c) ?0 run thresholds (v) 1.30 1.35 150 1871 g11 1.25 1.20 0 50 100 ?5 25 75 125 1.40 frequency (khz) 100 r t (k w ) 300 1000 1871 g12 10 100 200 1000 900 800 700 600 500 400 0 temperature ( c) ?0 275 gate frequency (khz) 280 290 295 300 325 310 0 50 75 1871 g13 285 315 320 305 ?5 25 100 125 150 temperature ( c) ?0 140 max sense threshold (mv) 145 150 155 160 25 0 25 50 1871 g14 75 100 125 150 temperature ( c) ?0 25 sense pin current ( a) 30 35 0 50 75 1871 g15 ?5 25 100 125 150 gate high v sense = 0v intv cc load (ma) 0 intv cc voltage (v) 5.2 30 50 80 1871 g16 5.1 5.0 10 20 40 60 70 v in = 7.5v v in (v) 0 5.1 intv cc voltage (v) 5.2 5.3 10 20 30 40 1871 g17 5.4 515 25 35 intv cc load (ma) 0 0 dropout voltage (mv) 50 150 200 250 500 350 5 10 1871 g18 100 400 450 300 15 20 150 c 75 c 125 c 25 c ?0 c 0 c
6 ltc1871 uu u pi fu ctio s run (pin 1): the run pin provides the user with an accurate means for sensing the input voltage and pro- gramming the start-up threshold for the converter. the falling run pin threshold is nominally 1.248v and the comparator has 100mv of hysteresis for noise immunity. when the run pin is below this input threshold, the ic is shut down and the v in supply current is kept to a low value (typ 10 m a). the absolute maximum rating for the voltage on this pin is 7v. i th (pin 2): error amplifier compensation pin. the cur- rent comparator input threshold increases with this control voltage. nominal voltage range for this pin is 0v to 1.40v. fb (pin 3): receives the feedback voltage from the external resistor divider across the output. nominal voltage for this pin in regulaton is 1.230v. freq (pin 4): a resistor from the freq pin to ground programs the operating frequency of the chip. the nomi- nal voltage at the freq pin is 0.6v. mode/sync (pin 5): this input controls the operating mode of the converter and allows for synchronizing the operating frequency to an external clock. if the mode/ sync pin is connected to ground, burst mode operation is enabled. if the mode/sync pin is connected to intv cc , or if an external logic-level synchronization signal is applied to this input, burst mode operation is disabled and the ic operates in a continuous mode. gnd (pin 6): ground pin. gate (pin 7): gate driver output. i ntv cc (pin 8): the internal 5.20v regulator output. the gate driver and control circuits are powered from this voltage. decouple this pin locally to the ic ground with a minimum of 4.7 m f low esr tantalum or ceramic capacitor. v in (pin 9): main supply pin. must be closely decoupled to ground. sense (pin 10): the current sense input for the control loop. connect this pin to the drain of the power mosfet for v ds sensing and highest efficiency. alternatively, the sense pin may be connected to a resistor in the source of the power mosfet. internal leading edge blanking is provided for both sensing methods.
7 ltc1871 block diagra w + + + 1.230v 85mv ov 50k ea uv to start-up control burst comparator s r q logic pwm latch current comparator 0.30v 1.230v 5.2v + 2.00v 1.230v slope 1.230v i loop fb i th + g m 3 mode/sync 5 freq 4 2 intv cc 8 ldo v-to-i osc v-to-i slope compensation bias and start-up control v in bias v ref i osc r loop + + c1 sense 10 gnd 1871 bd 6 gate intv cc gnd 7 v in 1.248v 9 run c2 1 0.6v
8 ltc1871 main control loop the ltc1871 is a constant frequency, current mode controller for dc/dc boost, sepic and flyback converter applications. the ltc1871 is distinguished from conven- tional current mode controllers because the current con- trol loop can be closed by sensing the voltage drop across the power mosfet switch instead of across a discrete sense resistor, as shown in figure 2. this sensing tech- nique improves efficiency, increases power density, and reduces the cost of the overall solution. operatio u to rise, which causes the current comparator c1 to trip at a higher peak inductor current value. the average inductor current will therefore rise until it equals the load current, thereby maintaining output regulation. the nominal operating frequency of the ltc1871 is pro- grammed using a resistor from the freq pin to ground and can be controlled over a 50khz to 1000khz range. in addition, the internal oscillator can be synchronized to an external clock applied to the mode/sync pin and can be locked to a frequency between 100% and 130% of its nominal value. when the mode/sync pin is left open, it is pulled low by an internal 50k resistor and burst mode operation is enabled. if this pin is taken above 2v or an external clock is applied, burst mode operation is disabled and the ic operates in continuous mode. with no load (or an extremely light load), the controller will skip pulses in order to maintain regulation and prevent excessive output ripple. the run pin controls whether the ic is enabled or is in a low current shutdown state. a micropower 1.248v refer- ence and comparator c2 allow the user to program the supply voltage at which the ic turns on and off (compara- tor c2 has 100mv of hysteresis for noise immunity). with the run pin below 1.248v, the chip is off and the input supply current is typically only 10 m a. an overvoltage comparator ov senses when the fb pin exceeds the reference voltage by 6.5% and provides a reset pulse to the main rs latch. because this rs latch is reset-dominant, the power mosfet is actively held off for the duration of an output overvoltage condition. the ltc1871 can be used either by sensing the voltage drop across the power mosfet or by connecting the sense pin to a conventional shunt resistor in the source of the power mosfet, as shown in figure 2. sensing the voltage across the power mosfet maximizes converter efficiency and minimizes the component count, but limits the output voltage to the maximum rating for this pin (36v). by connecting the sense pin to a resistor in the source of the power mosfet, the user is able to program output voltages significantly greater than 36v. c out v sw v sw 2a. sense pin connection for maximum efficiency (v sw < 36v) v out v in gnd l d + c out r s 1871 f02 2b. sense pin connection for precise control of peak current or for v sw > 36v v out v in gnd l d + gate gnd v in sense gate gnd v in sense figure 2. using the sense pin on the ltc1871 for circuit operation, please refer to the block diagram of the ic and figure 1. in normal operation, the power mosfet is turned on when the oscillator sets the pwm latch and is turned off when the current comparator c1 resets the latch. the divided-down output voltage is com- pared to an internal 1.230v reference by the error amplifier ea, which outputs an error signal at the i th pin. the voltage on the i th pin sets the current comparator c1 input threshold. when the load current increases, a fall in the fb voltage relative to the reference voltage causes the i th pin
9 ltc1871 operatio u programming the operating mode for applications where maximizing the efficiency at very light loads (e.g., <100 m a) is a high priority, the current in the output divider could be decreased to a few micro- amps and burst mode operation should be applied (i.e., the mode/sync pin should be connected to ground). in applications where fixed frequency operation is more critical than low current efficiency, or where the lowest output ripple is desired, pulse-skip mode operation should be used and the mode/sync pin should be connected to the intv cc pin. this allows discontinuous conduction mode (dcm) operation down to near the limit defined by the chips minimum on-time (about 175ns). below this output current level, the converter will begin to skip cycles in order to maintain output regulation. figures 3 and 4 show the light load switching waveforms for burst mode and pulse-skip mode operation for the converter in figure 1. burst mode operation burst mode operation is selected by leaving the mode/ sync pin unconnected or by connecting it to ground. in normal operation, the range on the i th pin corresponding to no load to full load is 0.30v to 1.2v. in burst mode operation, if the error amplifier ea drives the i th voltage below 0.525v, the buffered i th input to the current com- parator c1 will be clamped at 0.525v (which corresponds to 25% of maximum load current). the inductor current peak is then held at approximately 30mv divided by the power mosfet r ds(on) . if the i th pin drops below 0.30v, the burst mode comparator b1 will turn off the power mosfet and scale back the quiescent current of the ic to 250 m a (sleep mode). in this condition, the load current will be supplied by the output capacitor until the i th voltage rises above the 50mv hysteresis of the burst comparator. at light loads, short bursts of switching (where the aver- age inductor current is 20% of its maximum value) fol- lowed by long periods of sleep will be observed, thereby greatly improving converter efficiency. oscilloscope wave- forms illustrating burst mode operation are shown in figure 3. pulse-skip mode operation with the mode/sync pin tied to a dc voltage above 2v, burst mode operation is disabled. the internal, 0.525v buffered i th burst clamp is removed, allowing the i th pin to directly control the current comparator from no load to full load. with no load, the i th pin is driven below 0.30v, the power mosfet is turned off and sleep mode is invoked. oscilloscope waveforms illustrating this mode of operation are shown in figure 4. when an external clock signal drives the mode/sync pin at a rate faster than the chips internal oscillator, the oscillator will synchronize to it. in this synchronized mode, burst mode operation is disabled. the constant frequency associated with synchronized operation provides a more controlled noise spectrum from the converter, at the expense of overall system efficiency of light loads. 10 m s/div 1871 f03 figure 3. ltc1871 burst mode operation (mode/sync = 0v) at low output current figure 4. ltc1871 low output current operation with burst mode operation disabled (mode/sync = intv cc ) v out 50mv/div i l 5a/div v in = 3.3v v out = 5v i out = 500ma mode/sync = 0v (burst mode operation) v out 50mv/div i l 5a/div v in = 3.3v v out = 5v i out = 500ma mode/sync = intv cc (pulse-skip mode) 2 m s/div 1871 f04
10 ltc1871 applicatio s i for atio wu uu when the oscillators internal logic circuitry detects a synchronizing signal on the mode/sync pin, the internal oscillator ramp is terminated early and the slope compen- sation is increased by approximately 30%. as a result, in applications requiring synchronization, it is recommended that the nominal operating frequency of the ic be pro- grammed to be about 75% of the external clock frequency. attempting to synchronize to too high an external fre- quency (above 1.3f o ) can result in inadequate slope com- pensation and possible subharmonic oscillation (or jitter). the external clock signal must exceed 2v for at least 25ns, and should have a maximum duty cycle of 80%, as shown in figure 5. the mosfet turn on will synchronize to the rising edge of the external clock signal. to charge and discharge an internal oscillator capacitor. a graph for selecting the value of r t for a given operating frequency is shown in figure 6. figure 6. timing resistor (r t ) value figure 5. mode/sync clock input and switching waveforms for synchronized operation 1871 f05 2v to 7v mode/ sync gate i l t min = 25ns 0.8t d = 40% t t = 1/f o frequency (khz) 100 r t (k ) 300 1000 1871 f06 10 100 200 1000 900 800 700 600 500 400 0 programming the operating frequency the choice of operating frequency and inductor value is a tradeoff between efficiency and component size. low frequency operation improves efficiency by reducing mosfet and diode switching losses. however, lower frequency operation requires more inductance for a given amount of load current. the ltc1871 uses a constant frequency architecture that can be programmed over a 50khz to 1000khz range with a single external resistor from the freq pin to ground, as shown in figure 1. the nominal voltage on the freq pin is 0.6v, and the current that flows into the freq pin is used intv cc regulator bypassing and operation an internal, p-channel low dropout voltage regulator pro- duces the 5.2v supply which powers the gate driver and logic circuitry within the ltc1871, as shown in figure 7. the intv cc regulator can supply up to 50ma and must be bypassed to ground immediately adjacent to the ic pins with a minimum of 4.7 m f tantalum or ceramic capacitor. good bypassing is necessary to supply the high transient currents required by the mosfet gate driver. for input voltages that dont exceed 7v (the absolute maximum rating for this pin), the internal low dropout regulator in the ltc1871 is redundant and the intv cc pin can be shorted directly to the v in pin. with the intv cc pin shorted to v in , however, the divider that programs the regulated intv cc voltage will draw 10 m a of current from the input supply, even in shutdown mode. for applications that require the lowest shutdown mode input supply current, do not connect the intv cc pin to v in . regardless of whether the intv cc pin is shorted to v in or not, it is always necessary to have the driver circuitry bypassed with a 4.7 m f tantalum or low esr ceramic capacitor to ground immediately adjacent to the intv cc and gnd pins. in an actual application, most of the ic supply current is used to drive the gate capacitance of the power mosfet.
11 ltc1871 applicatio s i for atio wu uu as a result, high input voltage applications in which a large power mosfet is being driven at high frequencies can cause the ltc1871 to exceed its maximum junction temperature rating. the junction temperature can be estimated using the following equations: i q(tot) ? i q + f ? q g p ic = v in ? (i q + f ? q g ) t j = t a + p ic ? r th(ja) the total quiescent current i q(tot) consists of the static supply current (i q ) and the current required to charge and discharge the gate of the power mosfet. the 10-pin msop package has a thermal resistance of r th(ja) = 120 c/w. as an example, consider a power supply with v in = 5v and v o = 12v at i o = 1a. the switching frequency is 500khz, and the maximum ambient temperature is 70 c. the power mosfet chosen is the irf7805, which has a maximum r ds(on) of 11m w (at room temperature) and a maximum total gate charge of 37nc (the temperature coefficient of the gate charge is low). i q(tot) = 600 m a + 37nc ? 500khz = 19.1ma p ic = 5v ? 19.1ma = 95mw t j = 70 c + 120 c/w ? 95mw = 81.4 c this demonstrates how significant the gate charge current can be when compared to the static quiescent current in the ic. to prevent the maximum junction temperature from being exceeded, the input supply current must be checked when operating in a continuous mode at high v in . a tradeoff between the operating frequency and the size of the power mosfet may need to be made in order to maintain a reliable ic junction temperature. prior to lowering the operating frequency, however, be sure to check with power mosfet manufacturers for their latest-and-great- est low q g , low r ds(on) devices. power mosfet manu- facturing technologies are continually improving, with newer and better performance devices being introduced almost yearly. output voltage programming the output voltage is set by a resistor divider according to the following formula: vv r r o =+ ? ? ? ? 1 230 1 2 1 . the external resistor divider is connected to the output as shown in figure 1, allowing remote voltage sensing. the resistors r1 and r2 are typically chosen so that the error figure 7. bypassing the ldo regulator and gate driver supply + + 1.230v r2 r1 p-ch 5.2v driver gate c vcc 4.7 f c in input supply 2.5v to 30v gnd place as close as possible to device pins m1 1871 f07 intv cc v in gnd logic
12 ltc1871 applicatio s i for atio wu uu caused by the current flowing into the fb pin during normal operation is less than 1% (this translates to a maximum value of r1 of about 250k). programming turn-on and turn-off thresholds with the run pin the ltc1871 contains an independent, micropower volt- age reference and comparator detection circuit that re- mains active even when the device is shut down, as shown in figure 8. this allows users to accurately program an input voltage at which the converter will turn on and off. the falling threshold voltage on the run pin is equal to the internal reference voltage of 1.248v. the comparator has 100mv of hysteresis to increase noise immunity. the turn-on and turn-off input voltage thresholds are programmed using a resistor divider according to the following formulas: vv r r vv r r in off in on () () . . =+ ? ? ? ? =+ ? ? ? ? 1 248 1 2 1 1 348 1 2 1 the resistor r1 is typically chosen to be less than 1m. for applications where the run pin is only to be used as a logic input, the user should be aware of the 7v absolute maximum rating for this pin! the run pin can be connected to the input voltage through an external 1m resistor, as shown in figure 8c, for always on operaton. + run comparator v in run r2 r1 input supply optional filter capacitor + gnd 1871 f8a bias and start-up control 1.248v power reference 6v figure 8b. on/off control using external logic figure 8c. external pull-up resistor on run pin for always on operation figure 8a. programming the turn-on and turn-off thresholds using the run pin + run comparator 1.248v 1871 f08b run 6v external logic control + run comparator v in run r2 1m input supply + gnd 1.248v 1871 f08c 6v
13 ltc1871 applicatio s i for atio wu uu application circuits a basic ltc1871 application circuit is shown in figure 1. external component selection is driven by the characteristics of the load and the input supply. the first topology to be analyzed will be the boost converter, followed by sepic (single ended primary inductance converter). boost converter: duty cycle considerations for a boost converter operating in a continuous conduc- tion mode (ccm), the duty cycle of the main switch is: d vvv vv odin od = + + ? ? ? ? where v d is the forward voltage of the boost diode. for converters where the input voltage is close to the output voltage, the duty cycle is low and for converters that develop a high output voltage from a low voltage input supply, the duty cycle is high. the maximum output voltage for a boost converter operating in ccm is: v v d v omax in min max d () () = () 1 the maximum duty cycle capability of the ltc1871 is typically 92%. this allows the user to obtain high output voltages from low input supply voltages. boost converter: the peak and average input currents the control circuit in the ltc1871 is measuring the input current (either by using the r ds(on) of the power mosfet or by using a sense resistor in the mosfet source), so the output current needs to be reflected back to the input in order to dimension the power mosfet properly. based on the fact that, ideally, the output power is equal to the input power, the maximum average input current is: i i d the peak input current is i i d in max omax max in peak o max max () () () () : = =+ ? ? ? ? 1 1 21 c the maximum duty cycle, d max , should be calculated at minimum v in . boost converter: ripple current d i l and the c factor the constant c in the equation above represents the percentage peak-to-peak ripple current in the inductor, relative to its maximum value. for example, if 30% ripple current is chosen, then c = 0.30, and the peak current is 15% greater than the average. for a current mode boost regulator operating in ccm, slope compensation must be added for duty cycles above 50% in order to avoid subharmonic oscillation. for the ltc1871, this ramp compensation is internal. having an internally fixed ramp compensation waveform, however, does place some constraints on the value of the inductor and the operating frequency. if too large an inductor is used, the resulting current ramp ( d i l ) will be small relative to the internal ramp compensation (at duty cycles above 50%), and the converter operation will approach voltage mode (ramp compensation reduces the gain of the current loop). if too small an inductor is used, but the converter is still operating in ccm (near critical conduction mode), the internal ramp compensation may be inadequate to prevent subharmonic oscillation. to ensure good current mode gain and avoid subharmonic oscillation, it is recom- mended that the ripple current in the inductor fall in the range of 20% to 40% of the maximum average current. for example, if the maximum average input current is 1a, choose a d i l between 0.2a and 0.4a, and a value c between 0.2 and 0.4. boost converter: inductor selection given an operating input voltage range, and having chosen the operating frequency and ripple current in the inductor, the inductor value can be determined using the following equation: l v if d where i i d in min l max l omax max = d d= () () : c 1
14 ltc1871 remember that boost converters are not short-circuit protected. under a shorted output condition, the inductor current is limited only by the input supply capability. for applications requiring a step-up converter that is short- circuit protected, please refer to the applications section covering sepic converters. the minimum required saturation current of the inductor can be expressed as a function of the duty cycle and the load current, as follows: i i d l sat omax max () () 3+ ? ? ? ? 1 21 c the saturation current rating for the inductor should be checked at the minimum input voltage (which results in the highest inductor current) and maximum output current. boost converter: operating in discontinuous mode discontinuous mode operation occurs when the load current is low enough to allow the inductor current to run out during the off-time of the switch, as shown in figure 9. once the inductor current is near zero, the switch and diode capacitances resonate with the inductance to form damped ringing at 1mhz to 10mhz. if the off-time is long enough, the drain voltage will settle to the input voltage. depending on the input voltage and the residual energy in the inductor, this ringing can cause the drain of the power mosfet to go below ground where it is clamped by the body diode. this ringing is not harmful to the ic and it has not been shown to contribute significantly to emi. any attempt to damp it with a snubber will degrade the efficiency. boost converter: inductor core selection once the value for l is known, the type of inductor must be selected. high efficiency converters generally cannot af- ford the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite, molypermalloy or kool m m ? cores. actual core loss is independent of core size for a fixed inductor value, but is very dependent on the inductance selected. as inductance increases, core losses go down. unfortunately, increased inductance requires more turns of wire and therefore, copper losses will increase. generally, there is a tradeoff between core losses and copper losses that needs to be balanced. ferrite designs have very low core losses and are preferred at high switching frequencies, so design goals can con- centrate on copper losses and preventing saturation. ferrite core material saturates hard, meaning that the inductance collapses rapidly when the peak design current is exceeded. this results in an abrupt increase in inductor ripple current and consequently, output voltage ripple. do not allow the core to saturate! molypermalloy (from magnetics, inc.) is a very good, low cost core material for toroids, but is more expensive than ferrite. a reasonable compromise from the same manu- facturer is kool m m . boost converter: power mosfet selection the power mosfet serves two purposes in the ltc1871: it represents the main switching element in the power path, and its r ds(on) represents the current sensing ele- ment for the control loop. important parameters for the power mosfet include the drain-to-source breakdown voltage (bv dss ), the threshold voltage (v gs(th) ), the on- resistance (r ds(on) ) versus gate-to-source voltage, the gate-to-source and gate-to-drain charges (q gs and q gd , respectively), the maximum drain current (i d(max) ) and the mosfets thermal resistances (r th(jc) and r th(ja) ). the gate drive voltage is set by the 5.2v intv cc low drop regulator. consequently, logic-level threshold mosfets should be used in most ltc1871 applications. if low input voltage operation is expected (e.g., supplying power from applicatio s i for atio wu uu kool m m is a registered trademark of magnetics, inc. figure 9. discontinuous mode waveforms mosfet drain voltage 2v/div inductor current 2a/div v in = 3.3v v out = 5v i out = 200ma 2 m s/div 1871 f09
15 ltc1871 a lithium-ion battery or a 3.3v logic supply), then sublogic- level threshold mosfets should be used. pay close attention to the bv dss specifications for the mosfets relative to the maximum actual switch voltage in the application. many logic-level devices are limited to 30v or less, and the switch node can ring during the turn-off of the mosfet due to layout parasitics. check the switching waveforms of the mosfet directly across the drain and source terminals using the actual pc board layout (not just on a lab breadboard!) for excessive ringing. during the switch on-time, the control circuit limits the maximum voltage drop across the power mosfet to about 150mv (at low duty cycle). the peak inductor current is therefore limited to 150mv/r ds(on) . the rela- tionship between the maximum load current, duty cycle and the r ds(on) of the power mosfet is: rv d i ds on sense max max o max t () ( ) () + ? ? ? ? 1 1 2 c r the v sense(max) term is typically 150mv at low duty cycle, and is reduced to about 100mv at a duty cycle of 92% due to slope compensation, as shown in figure 10. the r t term accounts for the temperature coefficient of the r ds(on) of the mosfet, which is typically 0.4%/ c. figure 11 illustrates the variation of normalized r ds(on) over tempera ture for a typical power mosfet. another method of choosing which power mosfet to use is to check what the maximum output current is for a given r ds(on) , since mosfet on-resistances are available in discrete values. iv d r o max sense max max ds on t () () () = + ? ? ? ? 1 1 2 c r it is worth noting that the 1 C d max relationship between i o(max) and r ds(on) can cause boost converters with a wide input range to experience a dramatic range of maxi- mum input and output current. this should be taken into consideration in applications where it is important to limit the maximum current drawn from the input supply. calculating power mosfet switching and conduction losses and junction temperatures in order to calculate the junction temperature of the power mosfet, the power dissipated by the device must be known. this power dissipation is a function of the duty cycle, the load current and the junction temperature itself (due to the positive temperature coefficient of its r ds(on) ). as a result, some iterative calculation is normally required to determine a reasonably accurate value. since the con troller is using the mosfet as both a switching and a sensing element, care should be taken to ensure that the converter is capable of delivering the required load current over all operating conditions (line voltage and tempera- ture), and for the worst-case specifications for v sense(max) applicatio s i for atio wu uu duty cycle 0 maximum current sense voltage (mv) 100 150 0.8 1871 f10 50 0 0.2 0.4 0.5 1.0 200 figure 10. maximum sense threshold voltage vs duty cycle junction temperature ( c) ?0 r t normalized on resistance 1.0 1.5 150 1871 f11 0.5 0 0 50 100 2.0 figure 11. normalized r ds(on) vs temperature
16 ltc1871 and the r ds(on) of the mosfet listed in the manufacturers data sheet. the power dissipated by the mosfet in a boost converter is: p i d rd kv i d cf fet omax max ds on max t o omax max rss = ? ? ? ? + () () () . () 1 1 2 185 r the first term in the equation above represents the i 2 r losses in the device, and the second term, the switching losses. the constant, k = 1.7, is an empirical factor in- versely related to the gate drive current and has the dimen- sion of 1/current. from a known power dissipated in the power mosfet, its junction temperature can be obtained using the following formula: t j = t a + p fet ? r th(ja) the r th(ja) to be used in this equation normally includes the r th(jc) for the device plus the thermal resistance from the case to the ambient temperature (r th(ca) ). this value of t j can then be compared to the original, assumed value used in the iterative calculation process. boost converter: output diode selection to maximize efficiency, a fast switching diode with low forward drop and low reverse leakage is desired. the output diode in a boost converter conducts current during the switch off-time. the peak reverse voltage that the diode must withstand is equal to the regulator output voltage. the average forward current in normal operation is equal to the output current, and the peak current is equal to the peak inductor current. ii i d d peak l peak o max max ()() () ==+ ? ? ? ? 1 21 c the power dissipated by the diode is: p d = i o(max) ? v d and the diode junction temperature is: t j = t a + p d ? r th(ja) the r th(ja) to be used in this equation normally includes the r th(jc) for the device plus the thermal resistance from the board to the ambient temperature in the enclosure. remember to keep the diode lead lengths short and to observe proper switch-node layout (see board layout checklist) to avoid excessive ringing and increased dissipation. boost converter: output capacitor selection contributions of esr (equivalent series resistance), esl (equivalent series inductance) and the bulk capacitance must be considered when choosing the correct compo- nent for a given output ripple voltage. the effects of these three parameters (esr, esl and bulk c) on the output voltage ripple waveform are illustrated in figure 12e for a typical boost converter. the choice of component(s) begins with the maximum acceptable ripple voltage (expressed as a percentage of the output voltage), and how this ripple should be divided between the esr step and the charging/discharging d v. for the purpose of simplicity we will choose 2% for the maximum output ripple, to be divided equally between the esr step and the charging/discharging d v. this percentage ripple will change, depending on the require- ments of the application, and the equations provided below can easily be modified. for a 1% contribution to the total ripple voltage, the esr of the output capacitor can be determined using the following equation: esr v i cout o in peak 001 . () where: i i d in peak omax max () () =+ ? ? ? ? 1 21 c applicatio s i for atio wu uu
17 ltc1871 for the bulk c component, which also contributes 1% to the total ripple: c i vf out o max o 3 () . 001 for many designs it is possible to choose a single capaci- tor type that satisfies both the esr and bulk c require- ments for the design. in certain demanding applications, however, the ripple voltage can be improved significantly by connecting two or more types of capacitors in parallel. for example, using a low esr ceramic capacitor can minimize the esr step, while an electrolytic capacitor can be used to supply the required bulk c. once the output capacitor esr and bulk capacitance have been determined, the overall ripple voltage waveform should be verified on a dedicated pc board (see board layout section for more information on component place- ment). lab breadboards generally suffer from excessive series inductance (due to inter-component wiring), and these parasitics can make the switching waveforms look significantly worse than they would be on a properly designed pc board. the output capacitor in a boost regulator experiences high rms ripple currents, as shown in figure 12. the rms output capacitor ripple current is: ii vv v rms cout o max oinmin in min ()() () () ? note that the ripple current ratings from capacitor manu- facturers are often based on only 2000 hours of life. this makes it advisable to further derate the capacitor or to choose a capacitor rated at a higher temperature than required. several capacitors may also be placed in parallel to meet size or height requirements in the design. manufacturers such as nichicon, united chemicon and sanyo should be considered for high performance through- hole capacitors. the os-con semiconductor dielectric capacitor available from sanyo has the lowest product of esr and size of any aluminum electrolytic, at a somewhat higher price. in surface mount applications, multiple capacitors may have to be placed in parallel in order to meet the esr or rms current handling requirements of the application. aluminum electrolytic and dry tantalum capacitors are both available in surface mount packages. in the case of tantalum, it is critical that the capacitors have been surge tested for use in switching power supplies. an excellent choice is avx tps series of surface mount tantalum. also, ceramic capacitors are now available with extremely low esr, esl and high ripple current ratings. boost converter: input capacitor selection the input capacitor of a boost converter is less critical than the output capacitor, due to the fact that the inductor is in series with the input and the input current waveform is applicatio s i for atio wu uu v in ld sw 12a. circuit diagram 12b. inductor and input currents c out v out r l i in i l 12c. switch current i sw t on 12d. diode and output currents 12e. output voltage ripple waveform i o i d v out (ac) t off ? v esr ringing due to total inductance (board + cap) ? v cout figure 12. switching waveforms for a boost converter
18 ltc1871 continuous (see figure 12b). the input voltage source im- pedance determines the size of the input capacitor, which is typically in the range of 10 m f to 100 m f. a low esr capaci- tor is recommended, although it is not as critical as for the output capacitor. the rms input capacitor ripple current for a boost con- verter is: i v lf d rms cin in min max () () . = 03 please note that the input capacitor can see a very high surge current when a battery is suddenly connected to the input of the converter and solid tantalum capacitors can fail catastrophically under these conditions. be sure to specify surge-tested capacitors! burst mode operation and considerations the choice of mosfet r ds(on) and inductor value also determines the load current at which the ltc1871 enters burst mode operation. when bursting, the controller clamps the peak inductor current to approximately: i mv r burst peak ds on () () = 30 which represents about 20% of the maximum 150mv sense pin voltage. the corresponding average current depends upon the amount of ripple current. lower induc- tor values (higher d i l ) will reduce the load current at which burst mode operations begins, since it is the peak current that is being clamped. applicatio s i for atio wu uu table 1. recommended component manufacturers vendor components telephone web address avx capacitors (207) 282-5111 avxcorp.com bh electronics inductors, transformers (952) 894-9590 bhelectronics.com coilcraft inductors (847) 639-6400 coilcraft.com coiltronics inductors (407) 241-7876 coiltronics.com diodes, inc diodes (805) 446-4800 diodes.com fairchild mosfets (408) 822-2126 fairchildsemi.com general semiconductor diodes (516) 847-3000 generalsemiconductor.com international rectifier mosfets, diodes (310) 322-3331 irf.com irc sense resistors (361) 992-7900 irctt.com kemet tantalum capacitors (408) 986-0424 kemet.com magnetics inc toroid cores (800) 245-3984 mag-inc.com microsemi diodes (617) 926-0404 microsemi.com murata-erie inductors, capacitors (770) 436-1300 murata.co.jp nichicon capacitors (847) 843-7500 nichicon.com on semiconductor diodes (602) 244-6600 onsemi.com panasonic capacitors (714) 373-7334 panasonic.com sanyo capacitors (619) 661-6835 sanyo.co.jp sumida inductors (847) 956-0667 sumida.com taiyo yuden capacitors (408) 573-4150 t-yuden.com tdk capacitors, inductors (562) 596-1212 component.tdk.com thermalloy heat sinks (972) 243-4321 aavidthermalloy.com tokin capacitors (408) 432-8020 tokin.com toko inductors (847) 699-3430 tokoam.com united chemicon capacitors (847) 696-2000 chemi-com.com vishay/dale resistors (605) 665-9301 vishay.com vishay/siliconix mosfets (800) 554-5565 vishay.com vishay/sprague capacitors (207) 324-4140 vishay.com zetex small-signal discretes (631) 543-7100 zetex.com
19 ltc1871 the output voltage ripple can increase during burst mode operation if d i l is substantially less than i burst . this can occur if the input voltage is very low or if a very large inductor is chosen. at high duty cycles, a skipped cycle causes the inductor current to quickly decay to zero. however, because d i l is small, it takes multiple cycles for the current to ramp back up to i burst(peak) . during this inductor charging interval, the output capacitor must supply the load current and a significant droop in the output voltage can occur. generally, it is a good idea to choose a value of inductor d i l between 25% and 40% of i in(max) . the alternative is to either increase the value of the output capacitor or disable burst mode operation using the mode/sync pin. burst mode operation can be defeated by connecting the mode/sync pin to a high logic-level voltage (either with a control input or by connecting this pin to intv cc ). in this mode, the burst clamp is removed, and the chip can operate at constant frequency from continuous conduc- tion mode (ccm) at full load, down into deep discontinu- ous conduction mode (dcm) at light load. prior to skip- ping pulses at very light load (i.e., < 5% of full load), the controller will operate with a minimum switch on-time in dcm. pulse skipping prevents a loss of control of the output at very light loads and reduces output voltage ripple. efficiency considerations: how much does v ds sensing help? the efficiency of a switching regulator is equal to the output power divided by the input power ( 100%). per- cent efficiency can be expressed as: % efficiency = 100% C (l1 + l2 + l3 + ), where l1, l2, etc. are the individual loss components as a percentage of the input power. it is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. although all dissipative elements in the circuit produce losses, four main sources usually account for the majority of the losses in ltc1871 application circuits: 1. the supply current into v in . the v in current is the sum of the dc supply current i q (given in the electrical characteristics) and the mosfet driver and control currents. the dc supply current into the v in pin is typically about 550 m a and represents a small power loss (much less than 1%) that increases with v in . the driver current results from switching the gate capaci- tance of the power mosfet; this current is typically much larger than the dc current. each time the mosfet is switched on and then off, a packet of gate charge q g is transferred from intv cc to ground. the resulting dq/dt is a current that must be supplied to the intv cc capacitor through the v in pin by an external supply. if the ic is operating in ccm: i q(tot) ? i q = f ? q g p ic = v in ? (i q + f ? q g ) 2. power mosfet switching and conduction losses. the technique of using the voltage drop across the power mosfet to close the current feedback loop was chosen because of the increased efficiency that results from not having a sense resistor. the losses in the power mosfet are equal to: p i d rd kv i d cf fet omax max ds on max t o omax max rss = ? ? ? ? + () () . () 1 1 2 185 r the i 2 r power savings that result from not having a discrete sense resistor can be calculated almost by inspection. p i d rd r sense omax max sense max () () = ? ? ? ? 1 2 to understand the magnitude of the improvement with this v ds sensing technique, consider the 3.3v input, 5v output power supply shown in figure 1. the maximum load current is 7a (10a peak) and the duty cycle is 39%. assuming a ripple current of 40%, the peak inductor current is 13.8a and the average is 11.5a. with a maximum sense voltage of about 140mv, the sense applicatio s i for atio wu uu
20 ltc1871 resistor value would be 10m w , and the power dissi- pated in this resistor would be 514mw at maximum output current. assuming an efficiency of 90%, this sense resistor power dissipation represents 1.3% of the overall input power. in other words, for this appli- cation, the use of v ds sensing would increase the efficiency by approximately 1.3%. for more details regarding the various terms in these equations, please refer to the section boost converter: power mosfet selection. 3. the losses in the inductor are simply the dc input current squared times the winding resistance. express- ing this loss as a function of the output current yields: p i d r r winding omax max w () () = ? ? ? ? 1 2 4. losses in the boost diode. the power dissipation in the boost diode is: p diode = i o(max) ? v d the boost diode can be a major source of power loss in a boost converter. for the 3.3v input, 5v output at 7a example given above, a schottky diode with a 0.4v forward voltage would dissipate 2.8w, which repre- sents 7% of the input power. diode losses can become significant at low output voltages where the forward voltage is a significant percentage of the output voltage. 5. other losses, including c in and c o esr dissipation and inductor core losses, generally account for less than 2% of the total additional loss. checking transient response the regulator loop response can be verified by looking at the load transient response. switching regulators gener- ally take several cycles to respond to an instantaneous step in resistive load current. when the load step occurs, v o immediately shifts by an amount equal to ( d i load )(esr), and then c o begins to charge or discharge (depending on the direction of the load step) as shown in figure 13. the regulator feedback loop acts on the resulting error amp output signal to return v o to its steady-state value. during this recovery time, v o can be monitored for overshoot or ringing that would indicate a stability problem. a second, more severe transient can occur when connect- ing loads with large (> 1 m f) supply bypass capacitors. the discharged bypass capacitors are effectively put in parallel with c o , causing a nearly instantaneous drop in v o . no regulator can deliver enough current to prevent this prob- lem if the load switch resistance is low and it is driven quickly. the only solution is to limit the rise time of the switch drive in order to limit the inrush current di/dt to the load. boost converter design example the design example given here will be for the circuit shown in figure 1. the input voltage is 3.3v, and the output is 5v at a maximum load current of 7a (10a peak). 1. the duty cycle is: d vvv vv odin od = + + ? ? ? ? = + + = .. . .% 50433 504 38 9 2. pulse-skip operation is chosen so the mode/sync pin is shorted to intv cc . 3. the operating frequency is chosen to be 300khz to reduce the size of the inductor. from figure 5, the resistor from the freq pin to ground is 80k. 4. an inductor ripple current of 40% of the maximum load current is chosen, so the peak input current (which is also the minimum saturation current) is: i i d a in peak o max max () () . . . =+ ? ? ? ? == 1 21 12 7 1039 13 8 c applicatio s i for atio wu uu i out 2a/div v out (ac) 100mv/div figure 13. load transient response for a 3.3v input, 5v output boost converter application, 0.7a to 7a step v in = 3.3v v out = 5v mode/sync = intv cc (pulse-skip mode) 100 m s/div 1871 f13
21 ltc1871 the inductor ripple current is: d= = = i i d a l o max max c . . . () 1 04 7 1039 46 and so the inductor value is: l v if d v a khz h in min l max = d ==m () . . . . 33 4 6 300 039 093 the component chosen is a 1 m h inductor made by sumida (part number cep125-h 1romh) which has a saturation current of greater than 20a. 5. with the input voltage to the ic bootstrapped to the output of the power supply (5v), a logic-level mosfet can be used. because the duty cycle is 39%, the maximum sense pin threshold voltage is reduced from its low duty cycle typical value of 150mv to approxi- mately 140mv. assuming a mosfet junction tempera- ture of 125 c, the room temperature mosfet r ds(on) should be less than: rv d i v a m ds on sense max max o max t () ( ) () . . . . . + ? ? ? ? = + ? ? ? ? =w 1 1 2 0 140 1039 1 04 2 715 68 c r the mosfet used was the fairchild fds7760a, which has a maximum r ds(on) of 8m w at 4.5v v gs , a bv dss of greater than 30v, and a gate charge of 37nc at 5v v gs . 6. the diode for this design must handle a maximum dc output current of 10a and be rated for a minimum reverse voltage of v out , or 5v. a 25a, 15v diode from on semiconductor (mbrb2515l) was chosen for its high power dissipation capability. 7. the output capacitor usually consists of a high valued bulk c connected in parallel with a lower valued, low esr ceramic. based on a maximum output ripple voltage of 1%, or 50mv, the bulk c needs to be greater than: c i vf a v khz f out out max out 3= =m () . . 001 7 0 01 5 300 466 the rms ripple current rating for this capacitor needs to exceed: ii vv v a vv v a rms cout o max oinmin in min ()() () () . . 3= = 7 533 33 5 to satisfy this high rms current demand, four 150 m f panasonic capacitors (eefueoj151r) are required. in parallel with these bulk capacitors, two 22 m f, low esr (x5r) taiyo yuden ceramic capacitors (jmk325bj226mm) are added for hf noise reduction. check the output ripple with a single oscilloscope probe connected directly across the output capacitor terminals, where the hf switching currents flow. 8. the choice of an input capacitor for a boost converter depends on the impedance of the source supply and the amount of input ripple the converter will safely tolerate. for this particular design and lab setup a 100 m f sanyo poscap (6tpc 100m), in parallel with two 22 m f taiyo yuden ceramic capacitors (jmk325bj226mm) is re- quired (the input and return lead lengths are kept to a few inches, but the peak input current is close to 20a!). as with the output node, check the input ripple with a single oscilloscope probe connected across the input capacitor terminals. pc board layout checklist 1. in order to minimize switching noise and improve output load regulation, the gnd pin of the ltc1871 should be connected directly to 1) the negative termi- nal of the intv cc decoupling capacitor, 2) the negative terminal of the output decoupling capacitors, 3) the source of the power mosfet or the bottom terminal of the sense resistor, 4) the negative terminal of the input capacitor and 5) at least one via to the ground plane applicatio s i for atio wu uu
22 ltc1871 applicatio s i for atio wu uu immediately adjacent to pin 6. the ground trace on the top layer of the pc board should be as wide and short as possible to minimize series resistance and induc- tance. 2. beware of ground loops in multiple layer pc boards. try to maintain one central ground node on the board and use the input capacitor to avoid excess input ripple for high output current power supplies. if the ground plane ltc1871 m1 v in 1871 f14 v out switch node is also the heat spreader for l1, m1, d1 l1 r t r c c c r3 j1 c in c out c vcc r1 r2 pseudo-kelvin signal ground connection true remote output sensing vias to ground plane r4 pin 1 c out bulk c low esr ceramic jumper d1 figure 14. ltc1871 boost converter suggested layout run i th fb freq mode/ sync sense v in intv cc gate gnd ltc1871 + r4 j1 10 9 8 7 6 1 2 3 4 5 c vcc pseudo-kelvin ground connection c in m1 d1 l1 v in gnd 1871 f15 v out switch node c out r c r1 r t bold lines indicate high current paths r2 c c r3 + figure 15. ltc1871 boost converter layout diagram
23 ltc1871 is to be used for high dc currents, choose a path away from the small-signal components. 3. place the c vcc capacitor immediately adjacent to the intv cc and gnd pins on the ic package. this capacitor carries high di/dt mosfet gate drive currents. a low esr and esl 4.7 m f ceramic capacitor works well here. 4. the high di/dt loop from the bottom terminal of the output capacitor, through the power mosfet, through the boost diode and back through the output capacitors should be kept as tight as possible to reduce inductive ringing. excess inductance can cause increased stress on the power mosfet and increase hf noise on the output. if low esr ceramic capacitors are used on the output to reduce output noise, place these capacitors close to the boost diode in order to keep the series inductance to a minimum. 5. check the stress on the power mosfet by measuring its drain-to-source voltage directly across the device terminals (reference the ground of a single scope probe directly to the source pad on the pc board). beware of inductive ringing which can exceed the maximum speci- fied voltage rating of the mosfet. if this ringing cannot be avoided and exceeds the maximum rating of the device, either choose a higher voltage device or specify an avalanche-rated power mosfet. not all mosfets are created equal (some are more equal than others). 6. place the small-signal components away from high frequency switching nodes. in the layout shown in figure 14, all of the small-signal components have been placed on one side of the ic and all of the power components have been placed on the other. this also allows the use of a pseudo-kelvin connection for the signal ground, where high di/dt gate driver currents flow out of the ic ground pin in one direction (to the bottom plate of the intv cc decoupling capacitor) and small-signal currents flow in the other direction. 7. if a sense resistor is used in the source of the power mosfet, minimize the capacitance between the sense pin trace and any high frequency switching nodes. the ltc1871 contains an internal leading edge blanking time of approximately 180ns, which should be ad- equate for most applications. 8. for optimum load regulation and true remote sensing, the top of the output resistor divider should connect independently to the top of the output capacitor (kelvin connection), staying away from any high dv/dt traces. place the divider resistors near the ltc1871 in order to keep the high impedance fb node short. 9. for applications with multiple switching power con- verters connected to the same input supply, make sure that the input filter capacitor for the ltc1871 is not shared with other converters. ac input current from another converter could cause substantial input voltage ripple, and this could interfere with the operation of the ltc1871. a few inches of pc trace or wire (l ? 100nh) between the c in of the ltc1871 and the actual source v in should be sufficient to prevent current sharing problems. sepic converter applications the ltc1871 is also well suited to sepic (single-ended primary inductance converter) converter applications. the sepic converter shown in figure 16 uses two inductors. the advantage of the sepic converter is the input voltage may be higher or lower than the output voltage, and the output is short-circuit protected. applicatio s i for atio wu uu figures 16. sepic topolgy and current flow + + + sw l2 c out r l v out v in c1 d1 l1 16a. sepic topology + + + r l v out v in d1 16c. current flow during switch off-time + + + r l v out v in v in v in 16b. current flow during switch on-time
24 ltc1871 the first inductor, l1, together with the main switch, resembles a boost converter. the second inductor, l2, together with the output diode d1, resembles a flyback or buck-boost converter. the two inductors l1 and l2 can be independent but can also be wound on the same core since identical voltages are applied to l1 and l2 throughout the switching cycle. by making l1 = l2 and winding them on the same core the input ripple is reduced along with cost and size. all of the sepic applications information that follows assumes l1 = l2 = l. sepic converter: duty cycle considerations for a sepic converter operating in a continuous conduc- tion mode (ccm), the duty cycle of the main switch is: d vv vvv od in o d = + ++ ? ? ? ? where v d is the forward voltage of the diode. for convert- ers where the input voltage is close to the output voltage the duty cycle is near 50%. the maximum output voltage for a sepic converter is: vvv d d v d o max in d max max d max () =+ () 1 1 1 the maximum duty cycle of the ltc1871 is typically 92%. sepic converter: the peak and average input currents the control circuit in the ltc1871 is measuring the input current (either using the r ds(on) of the power mosfet or by means of a sense resistor in the mosfet source), so the output current needs to be reflected back to the input in order to dimension the power mosfet properly. based on the fact that, ideally, the output power is equal to the input power, the maximum input current for a sepic converter is: ii d d the peak input current is ii d d in max o max max max in peak o max max max () () () () : = =+ ? ? ? ? 1 1 21 c the maximum duty cycle, d max , should be calculated at minimum v in . the constant c represents the fraction of ripple current in the inductor relative to its maximum value. for example, if 30% ripple current is chosen, then c = 0.30 and the peak current is 15% greater than the average. applicatio s i for atio wu uu figures 17. sepic converter switching waveforms 17a. input inductor current i in i l1 sw on sw off 17b. output inductor current i o i l2 17c. dc coupling capacitor current i o i in i c1 17e. output ripple voltage v out (ac) ? v esr ringing due to total inductance (board + cap) ? v cout 17d. diode current i o i d1
25 ltc1871 applicatio s i for atio wu uu it is worth noting here that sepic converters that operate at high duty cycles (i.e., that develop a high output voltage from a low input voltage) can have very high input cur- rents, relative to the output current. be sure to check that the maximum load current will not overload the input supply. sepic converter: inductor selection for most sepic applications the equal inductor values will fall in the range of 10 m h to 100 m h. higher values will reduce the input ripple voltage and reduce the core loss. lower inductor values are chosen to reduce physical size and improve transient response. like the boost converter, the input current of the sepic converter is calculated at full load current and minimum input voltage. the peak inductor current can be signifi- cantly higher than the output current, especially with smaller inductors and lighter loads. the following formu- las assume ccm operation and calculate the maximum peak inductor currents at minimum v in : ii vv v ii vv v l peak o max od in min l peak o max in min d in min 1 2 1 2 1 2 () () () () () () () =+ ? ? ? ? + =+ ? ? ? ? + c c the ripple current in the inductor is typically 20% to 40% (i.e., a range of c from 0.20 to 0.40) of the maximum average input current occurring at v in(min) and i o(max) and d i l1 = d i l2 . expressing this ripple current as a function of the output current results in the following equations for calculating the inductor value: l v if d in min l max = d () where ii d d l o max max max : () d=c 1 by making l1 = l2 and winding them on the same core, the value of inductance in the equation above is replace by 2l due to mutual inductance. doing this maintains the same ripple current and energy storage in the inductors. for example, a coiltronix ctx10-4 is a 10 m h inductor with two windings. with the windings in parallel, 10 m h inductance is obtained with a current rating of 4a (the number of turns hasnt changed, but the wire diameter has doubled). splitting the two windings creates two 10 m h inductors with a current rating of 2a each. therefore, substituting 2l yields the following equation for coupled inductors: ll v if d in min l max 12 2 == d () specify the maximum inductor current to safely handle i l(pk) specified in the equation above. the saturation current rating for the inductor should be checked at the minimum input voltage (which results in the highest inductor current) and maximum output current. sepic converter: power mosfet selection the power mosfet serves two purposes in the ltc1871: it represents the main switching element in the power path, and its r ds(on) represents the current sensing element for the control loop. important parameters for the power mosfet include the drain-to-source breakdown voltage (bv dss ), the threshold voltage (v gs(th) ), the on- resistance (r ds(on) ) versus gate-to-source voltage, the gate-to-source and gate-to-drain charges (q gs and q gd , respectively), the maximum drain current (i d(max) ) and the mosfets thermal resistances (r th(jc) and r th(ja) ). the gate drive voltage is set by the 5.2v intv cc low dropout regulator. consequently, logic-level threshold mosfets should be used in most ltc1871 applications. if low input voltage operation is expected (e.g., supplying power from a lithium-ion battery), then sublogic-level threshold mosfets should be used. the maximum voltage that the mosfet switch must sustain during the off-time in a sepic converter is equal to the sum of the input and output voltages (v o + v in ). as a result, careful attention must be paid to the bv dss speci- fications for the mosfets relative to the maximum actual switch voltage in the application. many logic-level devices are limited to 30v or less. check the switching waveforms directly across the drain and source terminals of the power
26 ltc1871 mosfet to ensure the v ds remains below the maximum rating for the device. during the mosfets on-time, the control circuit limits the maximum voltage drop across the power mosfet to about 150mv (at low duty cycle). the peak inductor current is therefore limited to 150mv/r ds(on) . the rela- tionship between the maximum load current, duty cycle and the r ds(on) of the power mosfet is: r v i vv v ds on sense max omax t od in min () () () () + ? ? ? ? + ? ? ? ? + 1 1 2 1 1 c r the v sense(max) term is typically 150mv at low duty cycle and is reduced to about 100mv at a duty cycle of 92% due to slope compensation, as shown in figure 8. the constant c in the denominator represents the ripple current in the inductors relative to their maximum current. for example, if 30% ripple current is chosen, then c = 0.30. the r t term accounts for the temperature coefficient of the r ds(on) of the mosfet, which is typically 0.4%/ c. figure 9 illus- trates the variation of normalized r ds(on) over tempera- ture for a typical power mosfet. another method of choosing which power mosfet to use is to check what the maximum output current is for a given r ds(on) since mosfet on-resistances are available in discrete values. i v r vv v o max sense max ds on t od in min () () () () + ? ? ? ? + ? ? ? ? + 1 1 2 1 1 c r calculating power mosfet switching and conduction losses and junction temperatures in order to calculate the junction temperature of the power mosfet, the power dissipated by the device must be known. this power dissipation is a function of the duty cycle, the load current and the junction temperature itself. as a result, some iterative calculation is normally required to determine a reasonably accurate value. since the con- troller is using the mosfet as both a switching and a sensing element, care should be taken to ensure that the converter is capable of delivering the required load current over all operating conditions (load, line and temperature) and for the worst-case specifications for v sense(max) and the r ds(on) of the mosfet listed in the manufacturers data sheet. the power dissipated by the mosfet in a sepic converter is: pi d d rd kv v i d d cf fet o max max max ds on max t in min o o max max max rss = ? ? ? ? ++ () () () () . () 1 1 2 185 r the first term in the equation above represents the i 2 r losses in the device and the second term, the switching losses. the constant k = 1.7 is an empirical factor inversely related to the gate drive current and has the dimension of 1/current. from a known power dissipated in the power mosfet, its junction temperature can be obtained using the following formula: t j = t a + p fet ?r th(ja) the r th(ja) to be used in this equation normally includes the r th(jc) for the device plus the thermal resistance from the board to the ambient temperature in the enclosure. this value of t j can then be used to check the original assumption for the junction temperature in the iterative calculation process. sepic converter: output diode selection to maximize efficiency, a fast-switching diode with low forward drop and low reverse leakage is desired. the output diode in a sepic converter conducts current during the switch off-time. the peak reverse voltage that the diode must withstand is equal to v in(max) + v o . the average forward current in normal operation is equal to the output current, and the peak current is equal to: ii vv v d peak o max od in min () () () =+ ? ? ? ? + + ? ? ? ? 1 2 1 c the power dissipated by the diode is: p d = i o(max) ? v d applicatio s i for atio wu uu
27 ltc1871 and the diode junction temperature is: t j = t a + p d ? r th(ja) the r th(ja) to be used in this equation normally includes the r th(jc) for the device plus the thermal resistance from the board to the ambient temperature in the enclosure. sepic converter: output capacitor selection because of the improved performance of todays electro- lytic, tantalum and ceramic capacitors, engineers need to consider the contributions of esr (equivalent series resis- tance), esl (equivalent series inductance) and the bulk capacitance when choosing the correct component for a given output ripple voltage. the effects of these three parameters (esr, esl, and bulk c) on the output voltage ripple waveform are illustrated in figure 17 for a typical coupled-inductor sepic converter. the choice of component(s) begins with the maximum acceptable ripple voltage (expressed as a percentage of the output voltage), and how this ripple should be divided between the esr step and the charging/discharging d v. for the purpose of simplicity we will choose 2% for the maximum output ripple, to be divided equally between the esr step and the charging/discharging d v. this percent- age ripple will change, depending on the requirements of the application, and the equations provided below can easily be modified. for a 1% contribution to the total ripple voltage, the esr of the output capacitor can be determined using the following equation: esr v i cout o d peak 001 . () where: ii vv v d peak o max od in min () () () =+ ? ? ? ? + + ? ? ? ? 1 2 1 c for the bulk c component, which also contributes 1% to the total ripple: c i vf out o max o 3 () . 001 for many designs it is possible to choose a single capaci- tor type that satisfies both the esr and bulk c require- ments for the design. in certain demanding applications, however, the ripple voltage can be improved significantly by connecting two or more types of capacitors in parallel. for example, using a low esr ceramic capacitor can minimize the esr step, while an electrolytic or tantalum capacitor can be used to supply the required bulk c. once the output capacitor esr and bulk capacitance have been determined, the overall ripple voltage waveform should be verified on a dedicated pc board (see board layout section for more information on component place- ment). lab breadboards generally suffer from excessive series inductance (due to inter-component wiring), and these parasitics can make the switching waveforms look significantly worse than they would be on a properly designed pc board. the output capacitor in a sepic regulator experiences high rms ripple currents, as shown in figure 17. the rms output capacitor ripple current is: ii v v rms cout o max o in min ()() () = note that the ripple current ratings from capacitor manu- facturers are often based on only 2000 hours of life. this makes it advisable to further derate the capacitor or to choose a capacitor rated at a higher temperature than required. several capacitors may also be placed in parallel to meet size or height requirements in the design. manufacturers such as nichicon, united chemicon and sanyo should be considered for high performance through- hole capacitors. the os-con semiconductor dielectric capacitor available from sanyo has the lowest product of esr and size of any aluminum electrolytic, at a somewhat higher price. in surface mount applications, multiple capacitors may have to be placed in parallel in order to meet the esr or rms current handling requirements of the application. aluminum electrolytic and dry tantalum capacitors are both available in surface mount packages. in the case of tantalum, it is critical that the capacitors have been surge tested for use in switching power supplies. an excellent applicatio s i for atio wu uu
28 ltc1871 choice is avx tps series of surface mount tantalum. also, ceramic capacitors are now available with extremely low esr, esl and high ripple current ratings. sepic converter: input capacitor selection the input capacitor of a sepic converter is less critical than the output capacitor due to the fact that an inductor is in series with the input and the input current waveform is triangular in shape. the input voltage source impedance determines the size of the input capacitor which is typically in the range of 10 m f to 100 m f. a low esr capacitor is recommended, although it is not as critical as for the output capacitor. the rms input capacitor ripple current for a sepic con- verter is: ii rms cin l () =d 1 12 please note that the input capacitor can see a very high surge current when a battery is suddenly connected to the input of the converter and solid tantalum capacitors can fail catastrophically under these conditions. be sure to specify surge-tested capacitors! sepic converter: selecting the dc coupling capacitor the coupling capacitor c1 in figure 16 sees nearly a rectangular current waveform as shown in figure 17. during the switch off-time the current through c1 is i o (v o / v in ) while approximately C i o flows during the on-time. this current waveform creates a triangular ripple voltage on c1: d= ++ - v i cf v vvv cpp omax o in o d 1 1 () () the maximum voltage on c1 is then: vv v c max in cpp 1 1 2 () () =+ d - which is typically close to v in(max) . the ripple current through c1 is: ii vv v rms c o max od in min () ( ) () 1 = + the value chosen for the dc coupling capacitor normally starts with the minimum value that will satisfy 1) the rms current requirement and 2) the peak voltage requirement (typically close to v in ). low esr ceramic and tantalum capacitors work well here. sepic converter design example the design example given here will be for the circuit shown in figure 18. the input voltage is 5v to 15v and the output is 12v at a maximum load current of 1.5a (2a peak). 1. the duty cycle range is: d vv vvv to od in o d = + ++ ? ? ? ? = 45 5 71 4 .% .% 2. the operating mode chosen is pulse skipping, so the mode/sync pin is shorted to intv cc . 3. the operating frequency is chosen to be 300khz to reduce the size of the inductors; the resistor from the freq pin to ground is 80k. 4. an inductor ripple current of 40% is chosen, so the peak input current (which is also the minimum saturation current) is: ii vv v a l peak o max od in min 1 1 2 1 04 2 15 12 0 5 5 45 () () () . . . . =+ ? ? ? ? + =+ ? ? ? ? + = c the inductor ripple current is: d= == ii d d a l o max max max c .. . . . () 1 04 15 0 714 1 0 714 15 applicatio s i for atio wu uu
29 ltc1871 run i th fb freq mode/sync sense v in intv cc gate gnd 1 2 3 4 5 10 9 8 7 6 ltc1871 r t 80.6k 1% r1 12.1k 1% r2 105k 1% r3 1m c vcc 4.7 f x5r c in 47 f m1 c in , c out1 : kemet t495x476k020as c dc , c out2 : taiyo yuden tmk432bj106mm d1: international rectifier 30bq040 d1 l1* l2* r c 33k c c1 6.8nf c c2 47pf c out1 47 f 20v 2 v in 4.5v to 15v v out 12v 1.5a (2a peak) gnd 1871 f018a + c out2 10 f 25v x5r 2 l1, l2: bh electronics bh510-1007 (*coupled inductors) m1: international rectifier irf7811w c dc 10 f 25v x5r + figure 18a. 4.5v to 15v input, 12v/2a output sepic converter output current (a) 50 efficiency (%) 55 60 90 85 80 75 70 65 95 0.001 0.1 1 10 1871 f18b 45 0.01 100 v in = 4.5v v in = 15v v in = 12v v o = 12v mode = intv cc figure 18b. sepic efficiency vs output current applicatio s i for atio wu uu and so the inductor value is: l v if d k h in min l max = d ==m () . . 2 5 2 1 5 300 0 714 4 t he component chosen is a bh electronics bh510- 1007, which has a saturation current of 8a. 5. with an minimum input voltage of 5v, only logic-level power mosfets should be considered. because the maximum duty cycle is 71.4%, the maximum sense pin threshold voltage is reduced from its low duty cycle typical value of 150mv to approximately 120mv. assuming a mosfet junction temperature of 125 c, the room temperature mosfet r ds(on) should be less than: r v i vv v m ds on sense max omax t od in min () () () () . . .. . . + ? ? ? ? + ? ? ? ? + = ? ? ? ? + =w 1 1 2 1 1 012 15 1 12 15 1 12 5 5 1 12 7 c r for a sepic converter, the switch bv dss rating must be greater than v in(max) + v o , or 27v. this comes close to an irf7811w, which is rated to 30v, and has a maxi- mum room temperature r ds(on) of 12m w at v gs = 4.5v.
30 ltc1871 v out (ac) 200mv/div i out 0.5a/div figure 19. ltc1871 sepic converter load step response v in = 4.5v v out = 12v v out (ac) 200mv/div i out 0.5a/div v in = 15v v out = 12v 50 m s/div 1871 f19a 50 m s/div 1871 f19b applicatio s i for atio wu uu 6. the diode for this design must handle a maximum dc output current of 2a and be rated for a minimum reverse voltage of v in + v out , or 27v. a 3a, 40v diode from international rectifier (30bq040) is chosen for its small size, relatively low forward drop and acceptable reverse leakage at high temp. 7. the output capacitor usually consists of a high valued bulk c connected in parallel with a lower valued, low esr ceramic. based on a maximum output ripple voltage of 1%, or 120mv, the bulk c needs to be greater than: c i vf a v khz f out out max out 3= =m () . . . 001 15 0 01 12 300 41 the rms ripple current rating for this capacitor needs to exceed: ii v v a v v a rms cout o max o in min ()() () . . 3= = 15 12 5 23 to satisfy this high rms current demand, two 47 m f kemet capacitors (t495x476k020as) are required. as a result, the output ripple voltage is a low 50mv to 60mv. in parallel with these tantalums, two 10 m f, low esr (x5r) taiyo yuden ceramic capacitors (tmk432bj106mm) are added for hf noise reduction. check the output ripple with a single oscilloscope probe connected directly across the output capacitor termi- nals, where the hf switching currents flow. 8. the choice of an input capacitor for a sepic converter depends on the impedance of the source supply and the amount of input ripple the converter will safely tolerate. for this particular design and lab setup, a single 47 m f kemet tantalum capacitor (t495x476k020as) is ad- equate. as with the output node, check the input ripple with a single oscilloscope probe connected across the input capacitor terminals. if any hf switching noise is observed it is a good idea to decouple the input with a low esr, x5r ceramic capacitor as close to the v in and gnd pins as possible. 9. the dc coupling capacitor in a sepic converter is chosen based on its rms current requirement and must be rated for a minimum voltage of v in plus the ac ripple voltage. start with the minimum value which satisfies the rms current requirement and then check the ripple voltage to ensure that it doesnt exceed the dc rating. ii vv v a vv v a rms ci o max od in min () ( ) () . . . 3 + = + = 15 12 0 5 5 24 for this design a single 10 m f, low esr (x5r) taiyo yuden ceramic capacitor (tmk432bj106mm) is adequate.
31 ltc1871 typical applicatio s u 2.5v to 3.3v input, 5v/2a output boost converter run i th fb freq mode/sync sense v in intv cc gate gnd 1 2 3 4 5 10 9 8 7 6 ltc1871 r t 80.6k 1% r1 12.1k 1% r2 37.4k 1% c vcc 4.7 f x5r c in 47 f 6.3v m1 c in : sanyo poscap 6tpa47m c out1 : sanyo poscap 6tpb150m c out2 : taiyo yuden jmk316bj106ml c vcc : taiyo yuden lmk316bj475ml d1 l1 1.8 h r c 22k c c1 6.8nf c c2 47pf c out1 150 f 6.3v 2 v in 2.5v to 3.3v v out 5v 2a gnd 1871 ta01a + c out2 10 f 6.3v x5r 2 d1: international rectifier 30bq015 l1: toko ds104c2 b952as-1r8n m1: siliconix/vishay si9426 + output current (a) 65 efficiency (%) 95 100 60 55 90 75 85 80 70 0.001 0.1 1 10 1871 ta01b 50 0.01 output efficiency at 2.5v and 3.3v input
32 ltc1871 typical applicatio s u run i th fb freq mode/sync sense v in intv cc gate gnd 1 2 3 4 5 10 9 8 7 6 ltc1871 r t1 150k 5% r s1 0.007 1w ext clock input (200khz) r2 8.45k 1% c vcc1 4.7 f x5r c in2 2.2 f 35v x5r m1 d1 l2 5.6 h l5* 0.3 h c c1 47pf c fb1 47pf v in 18v to 27v gnd v out 28v 14a 1871 ta04 c out1 2.2 f 35v x5r 3 c out2 330 f 50v c in1 : sanyo 50mv330ax c in2, 3 : taiyo yuden gmk325bj225mn c out2, 4, 5 : sanyo 50mv330ax c out1, 3, 6 : taiyo yuden gmk325bj225mn c vcc1, 2 : taiyo yuden lmk316bj475ml l1 to l4: sumida cep125-5r6mc-hd l5: sumida cep125-0r3nc-nd d1, d2: on semiconductor mbr2045ct m1, m2: international rectifier irlz44ns r1 93.1k 1% l1 5.6 h *l5, c out5 and c out6 are an optional secondary filter to reduce output ripple from <500mv p-p to <100mv p-p + c out5 * 330 f 50v 4 c out6 * 2.2 f 35v x5r c in1 330 f 50v + run i th fb freq mode/sync sense v in intv cc gate gnd 1 2 3 4 5 10 9 8 7 6 ltc1871 r t2 150k 5% r3 12.1k 1% r c 22k r4 261k 1% c vcc2 4.7 f x5r c in3 2.2 f 35v x5r m2 d2 l4 5.6 h c c2 47pf c c3 6.8nf c fb2 47pf c out3 2.2 f 35v x5r 3 c out4 330 f 50v l3 5.6 h + + r s2 0.007 1w 18v to 27v input, 28v output, 400w 2-phase, low ripple, synchronized rf base station power supply (boost) run i th fb freq mode/sync sense v in intv cc gate gnd 1 2 3 4 5 10 9 8 7 6 ltc1871 r t 60.4k 1% r s 0.02 r4 127 1% r2 54.9k 1% r3 1.10k 1% c vcc 4.7 f 10v x5r c in1 1 f 16v x5r m1 d1 l1* r c 22k c c1 6.8nf c c2 100pf c dc1 4.7 f 16v x5r v in 5v to 12v v out1 12v 0.4a gnd v out2 ?2v 0.4a 1871 ta03 c out1 4.7 f 16v x5r 3 c out2 4.7 f 16v x5r 3 d1, d2: mbs120t3 l1 to l3: coiltronics vp1-0076 (*coupled inductors) m1: siliconix/vishay si4840 r1 127k 1% c in2 47 f 16v avx c dc2 4.7 f 16v x5r + l2* l3* d2 note: 1. v in uvlo + = 4.47v v in uvlo = 4.14v 5v to 12v input, 12v/0.2a output sepic converter with undervoltage lockout
33 ltc1871 4.5v to 28v input, 5v/2a output sepic converter with undervoltage lockout and soft-start typical applicatio s u run i th fb freq mode/sync sense v in intv cc gate gnd 1 2 3 4 5 10 9 8 7 6 ltc1871 r t 162k 1% c2 1 f x5r notes: 1. v in uvlo + = 4.17v v in uvlo = 3.86v 2. soft-start dv out /dt = 5v/6ms r4 49.9k 1% r3 154k 1% q1 r1 115k 1% r2 54.9k 1% c vcc 4.7 f 10v x5r c in1 2.2 f 35v x5r c in2 22 f 35v m1 d1 l1* l2* r c 12k c c1 8.2nf c1 4.7nf c c2 47pf r6 750 r5 100 c out1 330 f 6.3v v in 4.5v to 28v v out 5v 2a (3a to 4a peak) gnd 1871 ta02a + c out2 22 f 6.3v x5r c dc 2.2 f 25v x5r 3 + c in1 , c dc : taiyo yuden gmk325bj225mn c in2 : avx tpse226m035r0300 c out1 : sanyo 6tpb330m c out2 : taiyo yuden jmk325bj226mn c vcc : lmk316bj475ml d1: international rectifier 30bq040 l1, l2: bh electronics bh510-1007 (*coupled inductors) m1: siliconix/vishay si4840 q1: philips bc847bf soft-start v out 1v/div 1ms/div 1871 ta02b load step response at v in = 4.5v v out 100mv/div (ac) 250 m s/div 1871 ta02c i out 1a/div (dc) load step response at v in = 28v v out 100mv/div (ac) 250 m s/div 1871 ta02d i out 1a/div (dc) 2.2a 0.5a 2.2a 0.5a
34 ltc1871 typical applicatio s u 5v to 15v input, C 5v/5a output positive-to-negative converter with undervoltage lockout and level-shifted feedback run i th fb freq mode/sync sense v in intv cc gate gnd 1 2 3 4 5 10 9 8 7 6 ltc1871 r t 80.6k 1% r1 154k 1% r2 68.1k 1% c1 1nf c vcc 4.7 f 10v x5r c2 10nf r4 10k 1% r5 40.2k 1% r3 10k 1% 4 3 2 6 1 c in 47 f 16v x5r m1 c in : tdk c5750x5r1c476m c dc : tdk c5750x7r1e226m c out : tdk c5750x5r0j107m c vcc : taiyo yuden lmk316bj475ml d1 l1* l2* r c 10k c c1 10nf c c2 330pf v in 5v to 15v v out ?v 5a gnd 1871 ta05 c out 100 f 6.3v x5r 2 d1: on semiconductor mbrb2035ct l1, l2: coiltronics vp5-0053 (*3 windings in parallel for the primary, 3 in parallel for secondary) m1: international rectifier irf7822 c dc 22 f 25v x7r + lt1783
35 ltc1871 u package descriptio information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. ms package 10-lead plastic msop (reference ltc dwg # 05-08-1661) msop (ms) 1001 0.53 0.01 (.021 .006) seating plane 0.18 (.007) 1.10 (.043) max 0.17 0.27 (.007 ?.011) 0.13 0.05 (.005 .002) 0.86 (.034) ref 0.50 (.0197) typ 12 3 45 4.88 0.10 (.192 .004) 0.497 0.076 (.0196 .003) ref 8 9 10 7 6 3.00 0.102 (.118 .004) (note 3) 3.00 0.102 (.118 .004) note 4 note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.254 (.010) 0 ?6 typ detail ? detail ? gauge plane 5.23 (.206) min 3.2 ?3.45 (.126 ?.136) 0.889 0.127 (.035 .005) recommended solder pad layout without exposed pad option 3.05 0.38 (.0120 .0015) typ 0.50 (.0197) bsc
36 ltc1871 ? linear technology corporation 2001 sn1871 1871fs lt/tp 1001 2k ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear.com related parts part number description comments lt ? 1619 current mode pwm controller 300khz fixed frequency, boost, sepic, flyback topology ltc1624 current mode dc/dc controller so-8; 300khz operating frequency; buck, boost, sepic design; v in up to 36v ltc1700 no r sense synchronous step-up controller up to 95% efficiency, operation as low as 0.9v input ltc1872 sot-23 boost controller delivers up to 5a, 550khz fixed frequency, current mode lt1930 1.2mhz, sot-23 boost converter up to 34v output, 2.6v v in 16v, miniature design lt1931 inverting 1.2mhz, sot-23 converter positive-to-negative dc/dc conversion, miniature design ltc3401/ltc3402 1a/2a 3mhz synchronous boost converters up to 97% efficiency, very small solution, 0.5v v in 5v + run i th fb freq mode/sync sense v in intv cc gate gnd ltc1871 r t 120k f = 200khz *coiltronics vp5-0155 (primary = 3 windings in parallel) c1 4.7 f x5r + c in 220 f 16v tps c3 10 f 25v x5r irl2910 r s 0.012 c8 0.1 f d3 10bq060 5 v in 7v to 12v t1* 1, 2, 3 r c 82k c c1 1nf c c2 100pf c r 1nf r1 49.9k 1% r2 150k 1% d4 10bq060 6 d2 10bq060 4 + c4 10 f 25v x5r + c out 3.3 f 100v gnd v out1 ?4v 200ma v out2 ?2v 200ma + c5 10 f 25v x5r + 4 3 1871 ta06 2 6 1 10k r f1 10k 1% r f2 196k 1% c2 4.7 f 50v x5r + lt1783 high power slic supply with undervoltage lockout typical applicatio s u

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